Embodiments relate to a method of manufacturing a semiconductor device. As semiconductor devices become more highly integrated, the cell size in memory devices becomes smaller. Accordingly, the size of device isolation regions within memory cells must be minimized. However, the size of a device isolation region is dependent on a device isolation region formation process and an alignment between structures in a memory array. Therefore, the reduction of the size of the device isolation region is somewhat limited.
Device isolation regions may be formed using a shallow trench isolation (STI) process instead of a local oxidation of silicon (LOCOS) process. The switch may be motivated by a “bird's beak” phenomenon in the LOCOS process, while the STI process has excellent device isolation characteristics. In addition, a device isolation region with a narrow width can be obtained using the STI process.
The STI process includes forming a trench in a semiconductor substrate, filling the trench with an oxide layer, and performing a chemical mechanical polishing (CMP) process. However, when the device isolation layer is formed using the STI process, an electric field may be concentrated on an edge of the trench of the device isolation layer to form an undesirable transistor. This degrades device characteristics.